Best Practices for Reliable PCB Microstrip Design

A characteristic impedance is only a target until the board is built, and the gap between the number on your drawing and the number the fabricator measures is where most high-speed designs go wrong. The practices below close that gap by treating the stackup as a controlled structure, the reference plane as sacred, and the copper as a material that shrinks during processing. Every one of them shows up as a concrete input or a warning inside the PCB Microstrip Impedance Modeler.

Lock the stackup first. The microstrip formula depends on the dielectric height, so the thickness of the core or prepreg between the trace and the ground plane must be a value the laminate supplier guarantees, not a round number chosen for convenience. Ask for the finished dielectric height after lamination, because prepreg compresses under heat and pressure. When the tool asks for dielectric height, feed it the finished number, and keep that same value everywhere a microstrip crosses the board.

Make the reference plane continuous. The formula assumes an infinite solid ground plane below the trace, and the field follows the return current directly beneath the copper. If a moat, a split, or a keep-out cuts that plane, the return current detours around the gap, the effective loop widens, and the impedance spikes at exactly the frequency content of the signal edge. Route high-speed microstrips over uninterrupted plane, and never let a digital trace cross a split between two different power planes.

Compensate for etch. Wet etching removes copper from the sides as well as the top, so the finished trace is trapezoidal and narrower than the CAD width. Typical etch factors range from 0.8 to 0.95 of the drawn width depending on the layer, the copper weight, and the process. A 10 mil drawn trace may come back as 9 mils, which is enough to push a 50 ohm line up by a couple of ohms. The tool's width input should be the finished width unless your fabricator's impedance table already accounts for etch.

Count the solder mask. A solder mask layer over the trace has a dielectric constant near 3.3 and sits directly on the copper, so it loads the trace with extra capacitance and drags the impedance down by a few ohms. On dense boards where every ohm matters, the mask-defined impedance may differ from the bare-copper number this tool computes, and the fabricator's controlled-impedance stackup sheet is the reference that resolves the difference.

Stay inside the formula's validity window. The microstrip approximation holds for a width to height ratio between 0.1 and 3.0, and for dielectric constants between 1 and 15. A 50 ohm line on standard FR4 sits comfortably inside that range, but exotic thin dielectrics or very wide high-current traces can push a design outside it. The tool flags the w/h ratio when it leaves the window, which is the moment to switch from a formula to a field solver rather than trusting a number from the edge of the approximation.

Match the impedance budget to the driver. There is no single correct impedance; it is whatever the transmitter, the trace, and the receiver agree on. DDR and PCIe families commonly target 85 to 100 ohm differential pairs, USB 3.0 lines run near 90 ohms differential, and single-ended 50 ohm is the workhorse for RF and generic digital. Decide the target from the interface specification before the layout starts, enter it into the solve-width feature, and let the tool hand you the width instead of guessing.

Keep parallel microstrips apart. Adjacent edge-coupled traces share fringing field, which changes the per-line impedance even before a differential pair is considered. For loosely coupled single-ended lines, keep the spacing at least two or three trace widths; beyond that separation the coupling effect falls below a couple of percent and the single-line formula stays honest. Coupling is a feature when you want a differential pair, but it is a bug when you think you are routing two independent 50 ohm lines.

Verify against the fabricator's coupon. Every reputable board house measures impedance coupons on each production panel and reports the spread. Compare that report to the number this tool computed; a consistent offset across panels means the stackup differs from your assumption, usually in dielectric height or etch, and the fix is a stackup correction, not a routing scramble. The modeler is a design tool, and the coupon is the ground truth that closes the loop.

Document the geometry you used. The tool's copy-results button formats the trace width, dielectric height, copper thickness, dielectric constant, and every output into a single block, which belongs verbatim in the stackup note of the fabrication drawing. When the board comes back and a signal is marginal, that record tells you instantly whether the design intent was met or whether the geometry drifted. Controlled impedance is a discipline of numbers, and the discipline only works when the numbers are written down.